1. Field of the Invention.
The present invention relates to hybrid circuits and devices fabricated from superconductor materials combined with semiconductor devices that can be operated at low temperatures. More particularly the present invention relates to superconducting field effect transistor-like devices, sometimes called JOFETs for Josephson FETs or SFETs for superconducting FETs, and improvements to the utility of such devices when used in combination with low temperature CMOS devices in applications such as high speed, low power consumption memory and logic circuits. The present invention makes use of superconductive materials with low critical temperatures (T.sub.c .ltoreq.20K) as well as superconductive materials with high critical temperatures (T.sub.c &gt;20K).
More particularly, the present invention relates to improvements in cross-bar switching circuits which may be implemented using the superconductor circuits described herein.
2. Description of the Related Art.
A. Superconducting Switching Devices.
The discovery of superconductors whose critical temperatures are above liquid nitrogen temperature prompted interest in hybrid superconducting-semiconducting electronic circuit applications. The possibilities for using superconducting devices for interconnecting conventional semiconductor circuits and devices have been studied. See for example, "Superconductor-Semiconductor Hybrid Devices, Circuits and Systems," Kroger, et al., Proceedings of the IEEE, Vol. 77, No. 8, August 1989; T. van Duzer, "Superconductor-Semiconductor Hybrid Devices, Circuits and Systems," Cryogenics, Vol. 28, pp. 527-531 (1988); H. Kroger, "Josephson Devices Coupled by Semiconductor Links," IEEE Trans. Electron Devices, Vol. ED-27, pp. 2016-2126 (1980).
Prior art investigation and fabrication of hybrid three-terminal devices has led to the general conclusion that such devices are interesting but essentially useless in an engineering sense. The motivation for developing such devices has been to improve upon the gain and isolation available from conventional Josephson tunnel junctions, as well as to provide an active device which can perform all the conventional circuit functions as transistor circuits.
Superconducting Field Effect Transistors have been fabricated. FIG. 1 illustrates a superconducting FET structure. The superconducting FET is similar to conventional semiconductor FET structure, except that the source and drain must be superconductors. Devices constructed to date have a channel length in the range of 0.1 to 1.0 .mu.m. The function of a superconducting FET is similar to that of a conventional semiconductor FET, but it makes use of a conduction mechanism characteristic of superconductivity known as the proximity effect. Compared to the tunnel junctions thin barrier (10-60 nm), the greater channel length of the superconducting FET implies that the transport mechanism cannot be the tunnel effect. Superconducting electrons can diffuse into a doped semiconductor and make it weakly superconductive. This is called the proximity effect. The doped semiconductor need not be degeneratively doped since an inversion layer can also support a supercurrent and the material in which the inversion layer is formed need not be degeneratively doped.
Superconducting FETs function in analogy to semiconducting FETs in that the gate voltage controls the current flowing from the source to the drain. In superconducting FETs, the magnitude of a zero-voltage current can be controlled by the gate electrode. The drain of the device is either in a voltage state (on the order of tens of millivolts) or exactly at zero voltage. The SFET is unique in that it has a non-zero transconductance when the drain-to-source voltage is zero. No semiconductor FET has this property. One hope for such devices has been that they would provide fast switching with very low power dissipation. No matter which configuration is utilized, a minimum gate voltage is required to turn on or turn off a zero-voltage drain current. The only superconducting FETs studied to date were fabricated from low-temperature superconductors and are considered to be of little practical importance because they have zero power gain and do not produce an output voltage signal large enough to enable an SFET string of logic gates to be operated without additional logic level voltage restoration.
Many weak couplings of two superconductors show the Josephson effect. Such weak couplings include tunneling barriers, geometric constrictions in the superconductors themselves, and films of normal metals thinner than several hundreds of nanometers. These structures are called weak links.
For a normal metal weak link the critical current, I.sub.c, is a function of the normal carrier density in the link. I.sub.c is proportional to exp (-L/.xi.N) where L is the length of the link and .xi.N is the coherence length in the normal metal. .xi.N is given by: EQU .xi.N (h.sup.3 .mu./6.pi.m*ekT)1/2(3.pi..sup.2 n).sup.1/3
Where h is the Planck constant, .mu. is the carrier mobility, T is the absolute temperature, m* is the carrier effective mass, k is Boltzmann's constant, and n is the carrier density in the normal metal. Values of the coherence length in degeneratively doped semiconductors are a few hundred nanometers at 4.2K and lower temperatures.
A number of proposals have been made to develop superconducting three terminal devices analogous to semiconductors FETs. See for example, A. W. Kleinsasser and T. N. Jackson, "Superconductivity and field effect transistors," in Proc. 18th Int. Conf. on Low Temperature Physics (Kyoto); Jpn. J.Appl.Phys., Vol. 26, pp. 1545-1546, 1987; M. F. Millea, A. H. Silver, and L. D. Flesner, "Superconductivity contact to p. InAs," IEEE Trans. Magn., Vol. MAG-15, pp. 435-438, 1979; A. H. Silver, A. B. Chase, M. McCall, and M. F. Millea, "Superconductor-semiconductor device research," in Future Trends in Superconductive Electronics, B. S. Dever, C. M. Falco, J. H. Harris, and S. A. Wolf, Eds. New York, N.Y.: Am. Inst. of Physics, 1978, pp. 368-379; T. D. Clark, R. J. Prance, and A. D. C. Grassie, "Feasibility of hybrid Josephson field effect transistors," J.Appl.Phys., Vol. 51, pp. 2736-2745, 1980; A. W. Kleinsasser et al., "Semiconductor heterostructure weak links for superconducting FET applications," IEEE Trans. Magn., Vol. MAG-23, pp. 703-706, 1987; Z. Ivanov and T. Claeson, "A three terminal Josephson junction with a semiconducting two-dimensional electron gas layer," IEEE Trans. Magn., Vol. MAG-23, pp. 711-713, 1987; T. Nichino and U. Kawabe, "Realization of semiconductor-coupled superconducting transistor,"in Proc. 2nd Int. Symp. Foundations of Quantum Mechanics (Tokyo), pp. 231-240, 1986; T. Nichino, M. Miyake, Y. Harada, and U. Kawabe, "Three-terminal superconducting devices using a Si single-crystal film," IEEE Electron Device Lett., Vol. EDL-6, pp. 297-299, 1985; Z. Iranov, T. Claeson, and T. Anderson, "Three terminal Josephson junction with a semiconductor accumulation layer," in Proc. 18th Int. Conf. on Low Temperature Physics (Kyoto); Jpn. J. Appl. Phys., Vo.. 26, pp. 1617-1618, 1987; H. Takayangi and T. Kawakami, "Superconducting proximity effect in the native inversion layer on InAs," Phys. Rev. Lett., Vol. 55, pp. 2449-2452, Jun. 3, 1985. All these proposed devices function by changing the carrier density in the region under the gate, and thus the critical current in accordance with the equation given above for .xi.n. Actual reductions to practice have been made for structures using silicon, InAs or GaAs as the semiconductor portion of the device.
FIG. 2 represents the source-drain current-voltage (I-V) characteristics of a typical three-terminal superconducting FET. The inverse slope of the characteristics in the voltage state is the normal resistance R.sub.N of the device. The critical current I.sub.C is the maximum zero-voltage (Josephson) current which can flow between source and drain of the device. If the bias current I.sub.b is less than I.sub.C, then the voltage between source and drain is exactly zero. In a three-terminal superconducting FET, I.sub.C is controlled by the voltage applied to the gate electrode.
FIG. 3 is a schematic diagram of a typical superconductive FET inverter assuming the device works in the enhancement mode. As shown, the truth table for the device gate is:
______________________________________ Vin Vout ______________________________________ O V.sub.dd (&gt; V.sub.crit) V.sub.dd (&gt; V.sub.crit) I.sub.d R.sub.n ______________________________________ This circuit can be used in a string of logic gates (shown in phantom) only if I.sub.d R.sub.n &gt;V.sub.crit, that is, if the product of the bias current and normal resistance of the weak link is greater than V.sub.crit, the voltage required to induce a zero-voltage output in the following device. However, for all demonstrated devices in the prior art, I.sub.d R.sub.N is significantly less than V.sub.crit. This is why superconducting FETs of the prior art have been considered impractical.
In the circuit of FIG. 3, the bias current I.sub.d must be less than the maximum possible critical current I.sub.C in order to ensure that the device operates in the zero-voltage state. Therefore, a more general requirement for superconducting FETs is that I.sub.C R.sub.N &gt;V.sub.crit. For all known SFETs it has been observed that the I.sub.C R.sub.N product is significantly less than the required critical gate voltage of a subsequent device. Some studies have suggested that possible improvements to this situation might be obtained by fabricating superconductive FETs with high temperature superconductive elements. See for example, A. W. Kleinsasser and T. N. Jackson, "Prospects for proximity effect superconducting FETs," IEEE Trans. Magn., vol. MAG-25, pp. 1274-1277, 1989. These researchers conclude that a higher I.sub.C R.sub.N product might make possible the fabrication of devices with gain, but that such conclusion rests upon optimistic assumptions regarding material parameters and theory. Furthermore, despite extensive research, a number of theoretical questions persist concerning the operation of high temperature superconductive FETs which may effect whether practical FETs can be fabricated even with assumed improvements achieved with high temperature superconductor materials.
B. Crossbar Switches.
The term cross-bar switch as used herein applies generally to the class of devices or circuits which permit the arbitrary and selective connection of individual elements of two sets of devices or terminals, while preventing multiple connectors to or from any one element in either set. If, for example, the two sets of devices are designated P.sub.1, P.sub.2. . . , P.sub.N and M.sub.1, M.sub.2. . . M.sub.N each of which have associated ports, a cross-bar switch could be used to connect any one of the P.sub.i devices and M.sub.i devices while preventing a multiple connection to any of the P.sub.i devices or to any of the M.sub.i devices.
Referring now to FIG. 4, a typical prior art cross-bar switch array is illustrated. Cross-bar switching array A is formed of two orthogonal linear arrays of devices P.sub.i and M.sub.i. In the example illustrated, the P.sub.i devices could be multiple, parallel processes and the M.sub.i devices could be multiple, individually addressable memory devices or cells. The operation of the cross-bar switching matrix A must permit only a single connection to be made in any row and in any column at one time, and in keeping with the requirement that multiple connections to a single device are not allowed.
The manner in which this latter restriction is obtained is a matter of control over the switching matrix and can be accomplished in a variety of known ways. It is desirable for multiple connections to be made simultaneously so long as multiple connections are not made to or from a single port. The ports on the devices P.sub.i, M.sub.i can be unidirectional or bilateral. The cross-point switches S (FIG. 4) must be bilateral if bilateral functioning of the device is required.
There are several common examples of specific applications for cross-bar switching circuits. One arises in the field of telecommunications wherein each of the P.sub.i devices represent individual telephones or lines in one city and each of the M.sub.i devices represent individual telephones or lines in another city. For inter-city connections of these telephones, a cross-bar switch array as described above will perform the interconnection between telephones in the two cities while prohibiting party line connections. A second example relates to computer processing using multiple, parallel processor needing access to multiple memory devices. In such applications it is important that two different processors not be allowed to simultaneously access the same memory device to perform a rewrite function for example. The system would be very inefficient, however, if multiple simultaneous connections between processors and different memory devices were not possible.
The array shown in FIG. 4 is the most common form of cross-bar switching arrays. The vertical lines extending from devices M.sub.i and horizontal lines extending from devices P.sub.i do not connect, but pass over one another. A connection between these sets of lines is enabled through operation of one of the cross-bar switch elements S.sub.ij. For example, closure of switch S.sub.22 (FIG. 4) establishes a connection between processor P.sub.2 and memory M.sub.2. In practice, each of the switches S.sub.ij may include a small parasitic resistance, or an impedance which includes a small series inductance and a shunt PG,11 capacitance.
The practical ideal form of a switch S.sub.ij is one which approximates infinite impedance when open or "off" and zero impedance or a short circuit when closed or "on." In such embodiments, the signal from one P.sub.i device will reach the selected M.sub.j device or vice versa attenuated only by the parasitic impedance of the switch S.sub.ij neglecting the line resistance. The assumption of infinite impedance in an open or off position prevents attenuation of any signal from crosstalk.
An alternative, prior art cross-bar switching matrix design is illustrated in FIG. 5. This design is referred to as a Bedard array, and is characterized by the inverse nature of its operation as compared to the previously describes conventional array. In the Bedard array, the cross-bar array function is precisely the same as that previously described, but the operation of the cross-bar cells is inverted. In this form of an array, a connection between the M.sub.i device and the P.sub.j device is made only when the switch S.sub.ij is open, and the quiescent state of the array when no connections are made is when all switches S.sub.ij are closed.
In the Bedard array when a switch is closed signals between devices are shunted to ground. In order to effectively implement such a design it is necessary that the switch elements S.sub.ij have very low impedance when closed. Consequently, Josephson devices are naturally suited to serve as switching elements for this form of array because they have nearly zero resistance when closed provided that the applied junction current does not exceed the critical Josephson junction current. Conventional FET devices have nearly infinite impedance when open but non-zero resistance when closed or "on."
While the Bedard design with Josephson junction switching elements has advantages based upon intrinsic speed and ease of embedded control, it also has significant disadvantages. In this design, there are conduction paths to ground at all the cross-point cell connections for which no signal connection is intended at the unselected cross-points. This is because all switches at unselected cross-points are closed thereby permitting externally imposed currents to be spread over essentially the entire array. This leaves only a greatly reduced current available to be transmitted through the selected cross-point cell.
This condition could cause severe problems unless extraordinary measures are taken to control crosstalk. For an n by n array, a signal current introduced into the array from either the processor or memory sources will be reduced by a factor of approximately 2 n when it reaches the selected port. It is, therefore, possible that a signal 2 n times the desired output signal will cross over the output line or be adjacent to an output pin of the integrated circuit on which the array is fabricated. This requires that the crosstalk between output and input lines be kept much less than 1/2 n, which is a formidable task for arrays as small as 16 by 16.